1. Field of the Invention
This invention relates to a technology for testing semiconductor integrated circuit (IC) devices, and more particularly to a system and a method for automatically analyzing and managing loss factors in the test process.
2. Description of Related Art
After manufacture and prior to shipment, semiconductor IC devices are typically subjected to a number of tests to verify their performance and reliability. Among these is an electrical performance test.
The electrical performance test may include a DC test, an AC test and a functional test. The DC test is to verify DC characteristics of an IC device by performing an open/short test, measuring input currents, output voltages, power supply currents, etc. The AC test measures timings of an IC device by applying input pulse signals to input terminals of the device to check operational characteristics such as input/output propagation delay time (or access time), starting and finalized time of input and output signals, etc. In the functional test, test patterns generated from a pattern generator are transformed into pulse signals having a normal level and applied to a Device Under Test (DUT). The output signals from the DUT are compared to reference signals, for instance in the case of memory devices, to verify read/write functions and mutual interference of each of the memory cells during actual operation. Generally, a dynamic functional test combining the AC and functional tests is performed.
Conventional test systems for the electrical performance sort the IC devices into a number of “bin” categories according to the test results. For example, the semiconductor devices classified as “BIN 1” (i.e., bin category 1) are those that pass, or fall within the electrical performance specification, for all test items.
The test process constitutes a significant portion of the manufacture of semiconductor IC devices in terms of both time and expense. For testing mass-produced IC devices, expensive test systems and highly efficient handler systems are necessary. As the electrical performance of IC devices increasingly improves, the expense and time in the testing process grows higher and longer. As a result, loss factors found in the test process significantly affect the yield and productivity of IC devices more than expected before. The test process is commonly performed by lots in which a great number, e.g., one thousand (1,000) of IC devices are contained. The loss factors that may be caused in the lot test include time losses such as actual operation of the test system, loading, unloading, indexing, instantaneous stoppage, failure repair, lot change and re-testing.
However, in the conventional test process, the loss factor data are collected manually by operators or organized solely based on the practical experiences of test engineers. Accordingly, the loss factor data varies depending on the operators or engineers and therefore are not reliable. Furthermore, there exist loss factors that cannot be traced manually or empirically, which makes impossible the analytical collection and management of data concerning the loss factors. As the need of time-to-market of small-numbered and various kinds of semiconductor IC devices becomes more pressing, the improvement in the yield and productivity of IC devices increases in importance. Therefore, it would be highly desirable to reduce the loss factors and optimize the operational efficiency of test systems.
Moreover, it is necessary to efficiently and integrally control the test process performed by a tremendously large number of testers.